Analog-to-digital conversion converts analog signals into digital signals for digital processing in a digital signal processor or a microprocessor. Different analog-to-digital converter designs offer different performance characteristics including, e.g., the operating speed, the power consumption, the conversion accuracy, the area occupied by the ADC, noise and others.
For example, the high-speed readout, high resolution and low power consumption are important parameters to consider in designing CMOS image sensors, including ADCs used by CMOS image sensors.
There are various types of ADC architectures utilized and studied in CMOS image sensors. For example, a single-slope (SS) ADC using a single-slope ramp as a reference is currently commercialized for use but has difficulties in implementing a high-speed operation and high resolution. In addition, although a variety of techniques have been proposed to achieve low power consumption of the SS ADC, there are many limitations in improving power efficiency in terms of their operation algorithms.
As an alternate technique, a successive approximation register (SAR) ADC can also be used in CMOS image sensors and other circuitry. A SAR ADC implements an internal digital to analog converter (DAC) to produce reference signals and a series of comparisons to determine each bit of the converted result based on an algorithm capable of performing a high-speed operation while consuming low power. Unlike the SS ADC, the SAR ADC generates a reference voltage for performing analog-digital conversion of a pixel signal. Therefore, a reference voltage generator for generating the reference voltage needs to be installed at each column where each SAR ADC is arranged. Since the reference voltage generator has a size, however, the area is inevitably increased due to the presence of the reference voltage generator for the SAR ADC. Therefore, there are difficulties in integrating the SAR ADC in one column while having a size to satisfy a pixel pitch. If reducing the size of the reference voltage generator to fit into one column to satisfy the pixel pitch, such reduction in size has been reported to result in the degradation of the performance of the reference voltage generator and the overall performance of the SAR ADC. Thus, there is limitation to reduce the size of the reference voltage generator, and it difficult to reduce the area for the SAR ADC.
As an alternate technique, a SAR with a capacitor digital-to-analog converter (C-DAC) has been proposed, in which the digital-to-analog converter (DAC) inside the ADC is capacitive. The C-DAC SAR conducts an analog-digital converting of a current pixel signal using an analog-digital conversion result of a previous pixel signal, which can help to improve power efficiency and operation speed. In this case, however, more clocks may be used in comparison to the operation of the existing SAR ADC. Furthermore, the area of the C-DAC is doubled as the resolution bit is increased by one bit. Therefore, a large area may be required to manufacture a high-resolution ADC.